Typically occurs if the integration time is too short or if data cannot be written to the FIFO. When lit, it means that data is not being read fast enough from the DDC232. LD3-5: These three LEDs display the current 3 FSR bits (see below).LD2: When lit, the FPGA is in configuration, reading or sending states.LD1: When lit, the FPGA is in the idle state.When lit, a stable 120MHz clock is being generated (converts the on-board master clock from 100MHz). While the Nexys Video can be controlled entirely from software, the on-board switches, buttons and status LEDs on the Nexys Video have the following assignments: DIN (input): serial data input to the DDC used to daisy-chain other DDCs.DOUT (output): serial data stream of the 640-bit sequence (when in 20-bit precision mode) containing measurements of the 32 inputs.DVALID (output): active-low signal used to indicate that data is ready to be read on DOUT.DCLK (input): 20 MHz clocking signal used to time sending and reading of DOUT.RESET (input): Asynchronous active-low reset signal for the DDC to revert it to its power-up state.CLK_CFG (input): 20 MHz clocking signal used to time sending and reading of DIN_CFG.DIN_CFG (input): serial data stream of the 12-bit sequence used to set key parameters of the DDC, namely the FSR and measurement precision (16-bit or 20-bit).When this signal toggles, the integrator of each input switches. CONV (input): signal that controls integration, the time period of which is equal to the integration time.CLK (input): 10 MHz clocking signal that is used to time the internal operations of the DDC, including generation of DVALID.The role of each digital signal is described below: The DDC is housed on a compact custom circuit board manufactured by CosyLab (Ljubljana, Slovenia), where the charge collected by a photodiode is split across two DDC inputs to give 16 photodiodes per DDC. Each of the 32 inputs on the DDC has two integrators, allowing for zero-deadtime measurements: while one integrator digitises and transfers data, the other measures the input current. It is capable of measuring the currents of up to 32 photodiodes with an adjustable integration time (160μs–1s) and full-scale range (FSR, 12pC–350pC). DDC232 design features and demo given in this presentation.Ī Texas Instruments (Dallas, Texas, United States) DDC232CK (DDC) was chosen as the current-input analogue-to-digital converter for its speed, large dynamic range and low power requirements.First operational tests discussed in this presentation.UART interface between FPGA and PC discussed in this presentation.Results of simulation of FPGA design discussed here.I/O signals and operation of TI DDC232CK based on datasheet information.This website also contains several useful tutorials for learning FPGA design. Useful example on how to use the Nexys Video FTDI chip with libFTDI. C++ library used to communicate with the FTDI chip. Xilinx Integrated Logic Analyser manual.This contains essential information from which the FPGA design was created.
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